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FIFO memory chip CH424

Overview

CH424 is a 4K byte capacity FIFO memory chip. CH424 has two 8-bit passive parallel ports: Incoming W and Out R. CH424 is connected to the system bus of the MCU/DSP/MCU/MPU controller through 8-bit data lines and control lines such as read, write and chip select. It is suitable for connecting single chip microcomputer and single chip microcomputer, single chip microcomputer and DSP/MCU. The figure below is a block diagram of its general application.

Features

  • 4Kx 8 bit FIFO.
  • 8 bit parallel interface:
  • W end/entrance:8 bit Bidirectional tri-state data bus(WD7~WD0), chip select(W_CS), write operation(W_WR), read operation(W_RD);
  • R end/outlet:8 bit Bidirectional tri-state data bus(WD7~WD0), chip select(W_CS), read operation(W_RD), address(R_A0).
  • You can query the FIFO used space and the number of bytes of free space at any time, which is convenient for block reading and writing.
  • FIFO full status line FULL and FIFO empty status line EMPT are provided, active low.
  • Supports 5V supply voltage, 3.3V supply voltage and 3V supply voltage.
  • The LQFP-44 is available in a lead-free package, compatible withRoHS.
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relation files

file name file content
CH421DS1.PDF CH421 datasheet. Bidirectional buffer interface chip. The CH421 supports parallel port communication, asynchronous data exchange, no need to synchronization or waiting during read/write operations. The maximum transfer speed is not less than 7Mbytes per second. It can be used for 8-bit parallel port exchange data between two MCUs.
CH365DS1.PDF CH365 datasheet, PCI-SLAVE to communication interfaces chip, supports I/O port mapping, memory mapping, expansion ROM and interrupt, used for acquisition card/IO control card/communication card, etc.
CH367DS1.PDF CH367 datasheet, PCI-Express to 8-bit communication interfaces chip, supports I/O port mapping, expansion ROM and interrupt, used for acquisition card/IO control card/communication card, etc.