Application block diagram
- Parallel interface operation:
The CH351 chip provides a universal 8-bit passive parallel interface;
Can be easily hooked up to the system bus of various 8/16/32-bit MCU, DSP, MCU;
And it can coexist with multiple peripheral devices.
- Extended GPIO:
? 32 GPIO are divided into 4 groups, and a single parallel interface operation corresponds to a group of 8 GPIO pins;
? Inside the CH351 chip, each GPIO pin has a direction control bit and an internal output data bit, respectively;
? The extended GPIO pin input of the CH351 chip is compatible with CMOS and TTL levels, and has built-in weak pull-up resistors;
? Output CMOS level, compatible with TTL level, and low level 10mA high level 5mA drive capability.
The CH351 chip provides an active-low interrupt request output pin INT#;
? Can be connected to the interrupt input pin or common input pin of the microcontroller;
The CH351 will generate an interrupt request when the GPIO pin whose direction control bit is set to input is low.
The reset pin RST# of the CH351 chip is used to restore the CH351 to the default state;
When the RST# input is low, the internal output data bits of the X0~X31 pins all return to the state of 1;
And the direction control bits of X0~X31 all return to 0, that is, return to the input state.