32-bit 100M network MCU CH561


Overview

The CH561 is a 32-bit RISC reduced instruction set CPU with a default system clocked at 100 MHz. The on-chip integration supports 10/100M adaptive network interface (MAC + PHY) and built-in network PHY, which can be widely used in various networking control applications.

System Block Diagram

Characteristics

  • 32-bit RISC reduced instruction set, 100MHZ system frequency;
  • 64K CODE FLASH, 28K DATA FLASH, 32K SRAM;
  • 10/100M Ethernet interface (MAC + PHY);
  • 4 groups of 28-bit timers;
  • 10-bit ADC, 2 sets of SPI interface, 2 sets of serial ports;
  • Support low power sleep mode;
  • Package: LQFP64M;

Development materials

Program download method: network port or serial port download

  1. CH561DS1.PDF (CH561 Technical Manual)
  2. The program download software, WCHISPTool_Setup.exe
  3. CH561EVT.ZIP, including:
    • CH561 example program (C language)
    • CH561 TCP/IP network protocol stack library