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Ethernet controller chip CH390

Overview

CH390 is an industrial-grade Ethernet controller chip with its own 10/100M Ethernet Media Access Controller (MAC) and Physical Layer (PHY), supporting CAT3, 4, 5 for 10BASE-T and CAT5, 6 for 100BASE-TX connections, supporting HP Auto-MDIX, low-power consumption design, and complying with IEEE 802.3u specification. CH390 has built-in 16K bytes SRAM, supports 3.3V or 2.5V parallel interface and SPI serial interface for compatibility with various MCUs, MPUs, DSPs and other controllers.

Features

  • It comes with its own internal Ethernet Media Access Controller (MAC) and Physical Layer (PHY)
  • CH390L supports 8-bit and 16-bit parallel interface, CH390F supports 8-bit parallel interface, CH390H and CH390D support SPI serial interface.
  • Built-in unique Ethernet MAC address, no additional purchase or distribution, no external EEPROM.
  • CH390H/D provides SPI slave interface and supports SPI clock modes 0 and 3 with clock speeds up to 72MHz.
  • Integrated low-power 10/100M transceiver based on DSP algorithm implementation Transceiver.
  • Support Auto-MDIX to exchange TX/RX and automatically identify positive and negative signal lines.
  • Support 10BASE-T and 100BASE-TX and Auto-Negotiation.
  • Support UTP CAT5, CAT6 twisted pair cable, support 120 meters transmission distance.
  • Support wake-up frames, link state changes, and magic packet events for remote wake-up.
  • Support IEEE 802.3x flow control.
  • Support IPv4 TCP/UDP and IPv6 TCP/UDP checksum generation and checking.
  • Built-in LDO, support independent I/O interface power supply for different voltage processors or MCUs.
  • Built-in 50Ω matching resistor, built-in crystal oscillator capacitor, and with lower BOM cost.
  • Support optional external EEPROM configuration chip.
  • Small-size QFN20, QFN28, QFN32 and LQFP48 packages are available.

Package

package

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relation files

file name file content
CH182DS1.PDF CH182 datasheet, CH182 is an industrial grade 10/100M Ethernet PHY transceiver with Auto-MDIX support. CH182 internally includes Physical Coding Sublayer (PCS), Physical Media Access Layer (PMA), Twisted Pair Physical Medium Dependent (TP-PMD), 10BASE-TX encoder/decoder, Twisted Pair Media Attachment Unit (TPMAU), MII and RMII interfaces, and other modules required for Ethernet Transceiver functions.
CH392DS1.PDF CH392 datasheet. TCP/IP protocol stack chip, integrated 10M MAC and PHY transceiver, supports SPI/asynchronous serial port, built-in DHCP, ARP, UDP and TCP protocol firmware, supports MCU system to connect to Ethernet.
CH395DS1.PDF CH395 datasheet. TCP/IP Ethernet protocol stack chip, integrated 10/100M MAC and PHY transceiver, built-in DHCP, ARP, ICMP, IGMP, UDP and TCP protocol firmware, supports SPI/8-bit parallel port/asynchronous serial port and up to 8 sockets, supports MCU system to connect to Ethernet.
CH9121DS1.PDF CH9121 datasheet. Realize transparent transmission between UART and Ethernet. It supports UART and network configuration. It has built-in PHY, and supports serial device to connect to the network.
CH9120DS1.PDF CH9120 datasheet. CH9120 realizes bidirectional transparent transmission between UART and Ethernet, supports UART and network configuration. CH9120 has built-in 10M PHY, and supports serial device to connect to Ethernet.