32-bit Fast Ethernet MCU - CH561


CH561 is a CPU with 32-bit RISC-V reduced instruction sets. The system clock frequency is 100MHz by default. CH561 integrates 10/100M adaptive network interface (MAC+PHY) with built-in PHY. CH561 can be widely used in various network control applications.

System Block Diagram


  • 32-bit RISC reduced instruction sets, 100MHz system clock frequency.
  • 64KB CodeFlash, 28KB DATA Flash, 32KB SRAM.
  • 10/100M Ethernet interface (MAC+PHY).
  • 4 x 28-bit timers.
  • 10-bit ADC, 2 SPIs, 2 UARTs.
  • Low-power Sleep mode.
  • Package: LQFP64M.

Technical Resources

Downloading: network interface/UART

  1. CH561DS1.PDF (CH561 datasheet)
  2. Tool: WCHISPTool_Setup.exe
  3. CH561EVT.ZIP,contains CH561 reference routines (C programming language) CH561 TCP/IP network protocol stack library