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Ethernet PHY Transceiver Chip CH182

Overview

CH182 is an industrial grade 10/100M Ethernet PHY transceiver with Auto-MDIX support. CH182 internally includes Physical Coding Sublayer (PCS), Physical Media Access Layer (PMA), Twisted Pair Physical Medium Dependent (TP-PMD), 10BASE-TX encoder/decoder, Twisted Pair Media Attachment Unit (TPMAU), MII and RMII interfaces, and other modules required for Ethernet Transceiver functions.

The following figure shows the block diagram of CH182. Block diagram

Features

  • Low-power Ethernet physical layer transceiver PHYceiver implemented based on DSP algorithm.
  • Support downtime mode.
  • Support Auto-MDIX switching TX/RX and automatic identification of positive and negative signal lines.
  • Support 10BASE-T and 100BASE-TX and auto-negotiation.
  • Support both MII and RMII interface modes.
  • Support full-duplex and half-duplex operation.
  • Support UTP CAT5E and CAT6 twisted pair cable, support 120m transmission distance.
  • Built-in LDO, supports independent I/O interface power supply for different voltage processors or MCUs.
  • Built-in 50Ω impedance matching resistor, built-in capacitor required for 25MHz crystal oscillator, and streamlined peripheral circuitry.
  • Optional support for external 50MHz clock input.
  • Support WOL network wake-up.
  • Support interrupt function.
  • Support two types of network status LEDs.
  • Available in QFN24 and QFN32 packages.

Package

package Note: CH182F only supports RMII interface mode. All other CH182 contents are applicable to CH181 except where specifically marked.

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relation files

file name file content
CH182DS1.PDF CH182 datasheet, CH182 is an industrial grade 10/100M Ethernet PHY transceiver with Auto-MDIX support. CH182 internally includes Physical Coding Sublayer (PCS), Physical Media Access Layer (PMA), Twisted Pair Physical Medium Dependent (TP-PMD), 10BASE-TX encoder/decoder, Twisted Pair Media Attachment Unit (TPMAU), MII and RMII interfaces, and other modules required for Ethernet Transceiver functions.
CH390DS1.PDF CH390 Datasheet, CH390 is an industrial-grade Ethernet controller chip with its own 10/100M Ethernet Media Access Controller (MAC) and Physical Layer (PHY), supporting CAT3, 4, 5 for 10BASE-T and CAT5, 6 for 100BASE-TX connections, supporting HP Auto-MDIX, low-power consumption design, and complying with IEEE 802.3u specification. CH390 has built-in 16K bytes SRAM, supports 3.3V or 2.5V parallel interface and SPI serial interface for compatibility with various MCUs, MPUs, DSPs and other controllers.
CH395DS1.PDF CH395 datasheet. TCP/IP Ethernet protocol stack chip, integrated 10/100M MAC and PHY transceiver, built-in DHCP, ARP, ICMP, IGMP, UDP and TCP protocol firmware, supports SPI/8-bit parallel port/asynchronous serial port and up to 8 sockets, supports MCU system to connect to Ethernet.
CH392DS1.PDF CH392 datasheet. TCP/IP protocol stack chip, integrated 10M MAC and PHY transceiver, supports SPI/asynchronous serial port, built-in DHCP, ARP, UDP and TCP protocol firmware, supports MCU system to connect to Ethernet.
CH9121DS1.PDF CH9121 datasheet. Realize transparent transmission between UART and Ethernet. It supports UART and network configuration. It has built-in PHY, and supports serial device to connect to the network.
CH9120DS1.PDF CH9120 datasheet. CH9120 realizes bidirectional transparent transmission between UART and Ethernet, supports UART and network configuration. CH9120 has built-in 10M PHY, and supports serial device to connect to Ethernet.