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Ethernet Protocol Stack Chip CH394

Overview

CH394 is an Ethernet protocol stack management chip, which is used for Ethernet communication in MCU system. CH394 chip comes with 10/100M Ethernet Media Access Control (MAC) and Physical layer (PHY), which is fully compatible with IEEE802.3 protocol, and has built-in Ethernet protocol stack firmware such as IP, ARP, ICMP, IGMP, UDP and TCP. MCU system can conveniently communicate with the network through CH394 chip. CH394 supports Wake-on-LAN (WOL) and power-down mode. CH394Q provides SPI interface, CH394L provides SPI interface and 8-bit slave parallel interface. Controllers such as MCU/DSP/MPU can control CH394Q chip to communicate with Ethernet through SPI interface. Or through SPI interface or 8-bit parallel port to control CH394L chip for Ethernet communication. The following figure shows the application block diagram of CH394Q.

Features

  • Built-in Ethernet Media Access Control (MAC) and Physical layer (PHY)
  • Support 10/100M, full-duplex/half-duplex adaptation, and is compatible with 802.3 protocol
  • Support automatic conversion of MDI/MDIX lines
  • Built-in TCP/IP protocol suite. Support IPv4, ARP, ICMP, IGMP, UDP and TCP protocols
  • CH394Q supports 8 sockets and CH394L supports 4 sockets. Can transmit and receive data at the same time
  • Support MAC RAW mode and IP RAW mode (IP RAW mode is only supported by CH394L)
  • Provide a SPI slave interface (SPI mode 0 or 3) up to 40MHz, with the high bit coming first
  • The CH394L provides a high-speed 8-bit slave parallel interface that supports a parallel data bus connected to the microcontroller.
  • Support network Wake-on-LAN (WOL) and power-down mode
  • LED status display (Link, ACT, 10/100M, full-duplex/half-duplex, etc.)
  • Built-in 32KRAM can be used for Ethernet data transceiver, and each Socket transceiver buffer can be configured flexibly
  • LQFP48 lead-free package

Package

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relation files

file name file content
CH392DS1.PDF CH392 datasheet. TCP/IP protocol stack chip, integrated 10M MAC and PHY transceiver, supports SPI/asynchronous serial port, built-in DHCP, ARP, UDP and TCP protocol firmware, supports MCU system to connect to Ethernet.
CH395DS1.PDF CH395 datasheet. TCP/IP Ethernet protocol stack chip, integrated 10/100M MAC and PHY transceiver, built-in DHCP, ARP, ICMP, IGMP, UDP and TCP protocol firmware, supports SPI/8-bit parallel port/asynchronous serial port and up to 8 sockets, supports MCU system to connect to Ethernet.
CH390DS1.PDF CH390 Datasheet, CH390 is an industrial-grade Ethernet controller chip with its own 10/100M Ethernet Media Access Controller (MAC) and Physical Layer (PHY), supporting CAT3, 4, 5 for 10BASE-T and CAT5, 6 for 100BASE-TX connections, supporting HP Auto-MDIX, low-power consumption design, and complying with IEEE 802.3u specification. CH390 has built-in 16K bytes SRAM, supports 3.3V or 2.5V parallel interface and SPI serial interface for compatibility with various MCUs, MPUs, DSPs and other controllers.
CH182DS1.PDF CH182 datasheet, CH182 is an industrial grade 10/100M Ethernet PHY transceiver with Auto-MDIX support. CH182 internally includes Physical Coding Sublayer (PCS), Physical Media Access Layer (PMA), Twisted Pair Physical Medium Dependent (TP-PMD), 10BASE-TX encoder/decoder, Twisted Pair Media Attachment Unit (TPMAU), MII and RMII interfaces, and other modules required for Ethernet Transceiver functions.
CH9120DS1.PDF CH9120 datasheet. CH9120 realizes bidirectional transparent transmission between UART and Ethernet, supports UART and network configuration. CH9120 has built-in 10M PHY, and supports serial device to connect to Ethernet.
CH9121DS1.PDF CH9121 datasheet. Realize transparent transmission between UART and Ethernet. It supports UART and network configuration. It has built-in PHY, and supports serial device to connect to the network.